1. Field of the Invention
The present invention relates to an apparatus for forming a circuit pattern and, more particularly, to a pattern forming apparatus using a .mu.-STM and a method of forming a circuit pattern using the same.
2. Description of the Related Art
In the manufacture of large scale integrated circuits (LSI circuits) and the like, the step of forming various types of thin-film patterns such as a metal thin-film pattern as a wiring pattern is very important. Photolithography has been widely used for the formation of these patterns. In photolithography, a photosensitive resin film is exposed with ultraviolet rays, X-rays, an electron beam, or the like, and is developed to form a resin pattern having a predetermined plane shape. A semiconductor layer or a metal thin film on which the resin pattern has been formed is then selectively etched by using this resin pattern as a mask so as to be processed into a desired pattern. That is, a pattern forming method by photolithography is an indirect method via the resin pattern formation.
On the other hand, a pattern forming method employing the following direct writing method is also known. In this method, an electron beam or an ion beam is radiated onto a substrate in an atmosphere of, e.g., a gaseous organometallic compound. With this operation, the organometallic compound is decomposed, and free metal particles are deposited on the irradiated portion of the substrate. Therefore, by scanning an electron beam or an ion beam, a metal thin-film pattern is formed on the substrate.
Currently, a pattern having a line width of 100 nm can be formed by these techniques. However, in order to increase the integration density of an LSI circuit, elements must be further miniaturized. In order to miniaturize elements, a patterning technique with a higher resolution is indispensable. Under the circumstances, studies for achieving higher fineness and precision have been made. For example, a direct writing method and lithography based on the principle of a scanning tunneling microscope (to be referred to as an STM hereinafter) have been proposed.
An STM and a pattern forming method based thereon will be described below.
An STM is designed to scanning-microscopically observe the arrangement of atoms on a surface of a solid substance by using a free electron wave (tunnel current) penetrating through the surface due to a tunnel effect. Of controllable waves, a free electron wave has the shortest wavelength, which is equal to about the interatomic distance in a solid substance. Therefore, by applying the principle of an STM to lithography or the like, a finer pattern than that obtained by a conventional method can be formed.
FIGS. 1A and 1B show a direct writing method based on the principle of an STM. Referring to FIG. 1A, reference numeral 1 denotes a substrate having a surface on which a pattern is to be formed; and 2, a needle-like chip electrode for flowing a tunnel current. The substrate 1 is placed in a gas atmosphere of an organometallic compound, and the chip electrode 2 is arranged near the surface of the substrate 1. When a tunnel current J.sub.T is caused to flow between the chip electrode 2 and the substrate 1, the organometallic compound adsorbed on the substrate surface is dissociated by the energy of the current, and the free metal is deposited as metal particles 3 on the surface of the substrate 1. Therefore, by scanning the chip electrode 2 in the direction indicated by an arrow as shown in FIG. 1B, a metal thin-film pattern can be formed on the surface of the substrate 1.
In addition to the direct writing method shown in FIGS. 1A and 1B, lithography using a tunnel current can be performed in a similar manner. In this case, a lift-off technique is normally used instead of selective etching.
In the pattern forming method using the chip electrode 2, the highest resolution can be obtained by using a tunnel current, as described above. However, this method may be performed by using a current in a field emission region which has a higher energy than a tunnel current. Especially, in pattern formation by lithography, a current in a field emission region is preferably used. In a direct writing method using a current in a field emission region, it is considered that a local plasma formed by field emission contributes to the deposition of metal particles.
In order to form a micropattern such as an LSI wiring pattern by a method using the above-described STM, the chip electrode 2 is required to be greatly reduced in size and to be scanned within a predetermined micro-area. For this reason, by applying an LSI process, a micro chip electrode is formed on a distal end of a cantilever which has 5 .mu.m of thickness and is formed within a region of 1 mm.times.5 .mu.m. In the following description, the device including such micro chip electrode designed to be scanned will be called a ".mu.-STM", regardless of whether a tunnel current or a current in a field emission region is used.
A known .mu.-STM is provided with an actuator having four bimorph structures arranged along the longitudinal direction of the actuator, each of the bimorph structures being used for scanning the chip electrode in the upward, downward, leftward or rightward direction.
Another known .mu.-STM of cantilever type is shown in FIGS. 2A, 2B, and 2C (disclosed in Third STM International Meeting).
Referring to FIG. 2A, reference numeral 4 denotes a substrate. A semiconductor substrate such as a silicon substrate is used as the substrate 4. X-direction actuators 5X and 5Y are arranged on the upper surface of the substrate 4. Both the actuators 5X and 5Y extend outward from a peripheral portion of the substrate 4. The distal ends of the actuators 5X and 5Y are integrated with each other, thereby forming a chip corner. A micro chip electrode 6 is formed upright on the surface of the chip corner. In addition, various wires 7X to 9X, 7Y to 9Y, and 10 are formed on the surface of the substrate 4.
FIG. 2B is a cross-sectional view of the actuators 5X and 5Y. As shown in FIG. 2B, each actuator is a multilayered member consisting of an SiO.sub.2 layer 11, an Al layer 12, a piezoelectric layer 13, an Al layer 14, a piezoelectric layer 15, and an Al+Au layer 16. As a piezoelectric substance, ZnO, lead zirconium titanate (Pb(Zr-Ti)O.sub.3), or the like is used. The Al layers 12 and 14 and the Au layer 16 constitute voltage applying electrodes. Voltages are applied to the piezoelectric layers 13 and 15 through these electrodes. Upon this voltage application, the piezoelectric layers 13 and 15 cause expansion and contraction deformation at a rate of about 240 .ANG. /v. Therefore, the deformations of the actuators 5X and 5Y are adjusted by controlling voltages to be applied, thus scanning the micro chip electrode 6 within a predetermined small range, not only in X-direction but also in Y- or Z-direction.
FIG. 2C is a plan view showing a wiring of the cantilever type .mu.-STM. As shown in FIG. 2C, various wires are formed on the surface of the substrate 4. The wires 7X, 8X, and 9X are respectively connected to the electrodes 16, 14, and 12 of the actuator 5X. The wires 7Y, 8Y, and 9Y are respectively connected to the electrodes 16, 14, and 12 of the actuator 5Y. The wire 10 is connected to the micro chip electrode 6. In addition, terminals 17X to 19X, 17Y to 19Y, and 20 are respectively formed on the proximal ends of the wires.
The above-described cantilever type .mu.-STM is manufactured on the basis of an LSI process. More specifically, the actuators 5X and 5Y as multilayered members each consisting of the SiO.sub.2 layer 11, the Al layer 12, the piezoelectric layer 13, the Al layer 14, the piezoelectric layer 15, and the Al+Au layer 16 are formed on a substrate 4 by using a technique such as CVD, sputtering, or PEP (photo-engraving process). In addition, the micro chip electrode 6 is formed. Thereafter, a portion of the substrate 4 is removed by etching so as to cause the actuators 5X and 5Y to protrude from the peripheral portion of the substrate 4, as shown in FIGS. 2A and 2C.
The micro chip electrode 6 is formed in the manner shown in FIGS. 3A, 3B, and 3C. More specifically, a spacer layer 21 consisting of a removable substance such as Cu, and a mask layer 22 consisting of Ti/W are formed on the piezoelectric layer 15 constituting each actuator. By performing PEP, an opening having a diameter of about 5.mu. is formed in the mask layer 22. The spacer layer 21 is then overetched by using the mask layer 22 as an etching mask, thus forming an undercut hole 23. As shown in FIG. 3B, the conical chip electrode 6 is formed in the undercut hole 23 by vacuum deposition of a metal such as Ta. Subsequently, the spacer layer 21 is etched to lift off the mask layer 22 and the Ta layer deposited thereon, as shown in FIG. 3C.
Currently, a pattern can be formed to have a line width on the order of 10 nm by employing the method using the .mu.-STM. However, for example, the following problems are posed when this method is applied to an LSI manufacturing process.
In the manufacture of LSI circuits, predetermined LSI circuits are respectively formed in a large number of LSI-chip regions on one wafer. If these LSI circuits are to be manufactured by a .mu.-STM having only one micro chip electrode, wiring patterns and the like must be sequentially formed on the large number of LSI-chip regions. Therefore, a very long period of time is required, and practical productivity cannot be obtained.